The present invention relates to a method for converting a logic circuit model specifically described at RT (Register Transfer) level into a high abstraction-level operation model including no concept of time.
In the conventional logic circuit design, an RT-level model based on logic synthesis is produced using a hardware description language (HDL) such as Verilog-HDL, and logic circuit blocks are designed and verified with such an RT-level model. However, simulation using the RT-level model is time-consuming because it is specifically described based on the clock and the like. It is therefore difficult to simulate a large-scale system.
For example, the following methods are conventionally disclosed for improved simulation speed: a method for eliminating a part of a logic circuit by partially fixing the inputs and registers according to the verification purposes (Japanese Laid-Open Publication No. 2001-22808); a method for integrating operations of a plurality of clocks that are not susceptible to an input/output signal into operation of one clock in a hardware model used in hardware-software cooperated simulation for connecting an instruction level simulator and a logic circuit simulator (Japanese Laid-Open Publication No. 10-187789); and a method for removing a clock signal from a logic circuit model in which the start and end of operations are defined (Japanese Laid-Open Publication No. 11-96196).
As a method for designing a system having logic circuits is disclosed a method for verifying the overall operation specification of the system based on a higher abstraction-level model and then refining the model in a stepwise manner (U.S. Pat. No. 5,870,588). High abstraction-level models used in such a design method are described in C language or the like and do not include the concept of time. Connection between such models is not implemented with a signal but with an instruction applied from block to bock of a logic circuit. In the simulation using such models, operations of the blocks are executed serially, not in parallel. Accordingly, if one block gives an instruction to another, the operation of the former block will not proceed until the operation of the latter is completed. The use of such high abstraction-level models thus enables the simulation without complicated scheduling based on the parallel operation. This improves the simulation speed and also enables the model to be produced in the early stages before a detailed specification at RL level is determined. As a result, in the early stages of design, the overall operation specification of the system can be verified and the system architecture can be reviewed by using statistical data such as the number of times each block is called. Accordingly, the system can be efficiently designed.
At the time of reusing the design resources, the models specifically described at RT-level may be present, but high abstraction-level models for use in verification of the operation specification may no longer be present. Accordingly, in order to reuse a block, a high abstraction-level model must be developed based on the specification or a specifically described model. Development and verification of such a model takes a great deal of time. Moreover, since both the specifically described model and the high abstraction-model model must be developed, mismatch of operation may possibly occur.
Of the aforementioned conventional methods for improved simulation speed, the method for partially fixing the inputs and registers would not produce a model having a sufficiently high abstraction model. Moreover, the method using only an instruction simulator for connection between blocks and the method in which the start and end of operations are defined are applicable only to the limited types of models.
It is an object of the present invention to provide a versatile method for converting a model of a logic circuit block specifically described at RT level into a high abstraction-level model for use in simulation for processing each block serially.
More specifically, according to one aspect of the present invention, a method for converting an RT-level model of a logic circuit block into a high abstraction-level operation model includes the steps of: setting one or more states of the logic circuit block as operation start states and operation end states by using input/output instruction information that represents a relation between an input/output instruction of the logic circuit block and an input/output signal corresponding to the input/output instruction; and analyzing operation of the logic circuit block. The operation analyzing step is conducted by selecting one input instruction to be analyzed from those included in the input/output instruction information, applying an input signal corresponding to the selected input instruction to the RT-level model that is in a first state selected from the operation start states, and analyzing the RT-level model and extracting an operation of the logic circuit block by varying the input signal, until the RT-level model reaches a second state of the operation end states. The operation analyzing step is repeatedly conducted for at least one or all combinations of the operation start state and the input instruction included in the input/output instruction information, and the operation model of the logic circuit block is produced based on the extracted operations.
According to the present invention, state transition of the logic circuit block according to a change in input signal caused by an input instruction, and an output instruction corresponding to a change in output signal are extracted based on the input/output instruction information that represents the relation between an input/output signal of the logic circuit block and a high abstraction-level input/output instruction. Based on the extracted result, the RT-level model can be converted into an operation model having no concept of time.
Preferably, the operation analyzing step includes the steps of producing a time series of one or more input signals corresponding to the instruction to be analyzed, producing a time series of an output signal by executing the RT-level model using the time series of the input signals until the RT-level model reaches the second state, extracting a state where the RT-level model reaches the second state as an operation of the logic circuit block, and comparing the time series of the output signal with the relation between an output instruction and an output signal corresponding thereto as defined in the input/output instruction information, and extracting the output instruction from those included in the input/output instruction information as an operation of the logic circuit block.
Preferably, the operation analyzing step includes the steps of producing at every clock one or more input signals corresponding to an input instruction included in the instruction to be analyzed, executing the RT-level model at every clock using the input signals, and producing an output signal at every clock, extracting at every clock a state where the RT-level model reaches the second state as an operation of the logic circuit block, and comparing the output signal with the relation between an output instruction and an output signal corresponding thereto as defined in the input/output instruction information, and extracting at every clock the output instruction from those included in the input/output instruction information as an operation of the logic circuit block.
Preferably, the input/output instruction information includes as an output instruction an output instruction with a response signal. The output instruction with the response signal is an instruction having both an output signal and an input signal associated therewith as a response signal thereof. In the operation analyzing step, when the output instruction with the response signal is extracted at one clock, operation of the RT-level model at a clock later than the one clock is analyzed by using the response signal produced by varying a value of the response signal corresponding to the output instruction with the response signal at a timing designated by the input/output instruction information.
Preferably, the input/output instruction information includes as an input instruction an input instruction with a response signal. The input instruction with the response signal is an instruction having both an input signal and an output signal associated therewith as a response signal thereof. In the operation analyzing step, when the input instruction with the response signal is selected at one clock as the instruction to be analyzed, operation of the RT-level model at a clock later than the one clock is analyzed by using the response signal produced based on a value of the response signal corresponding to the input instruction with the response signal, which varies at a timing designated by the input/output instruction information.
Preferably, the input/output instruction information includes as an output instruction an output instruction with a return value. The output instruction with the return value is an instruction having an input signal associated therewith as a return value. In the operation analyzing step, when operation of the RT-level model varies according to a value of the input signal serving as the return value of the output instruction, operation of the RT-level model is analyzed for every possible combination of values of the return value.
Preferably, the input/output instruction information includes as an input instruction an input instruction with a return value. The input instruction with the return value is an instruction having an output signal associated therewith as a return value. In the operation analyzing step, a value of the output signal at a clock designated by the input/output instruction information is extracted as the return value of the input instruction, and operation of the RT-level model is analyzed based on the extracted value.
Preferably, in the state setting step, a state where a state of the logic circuit block does not change in the absence of an input instruction or a state where a finite number of states of the logic circuit block are repeated in the absence of an input instruction are set as the operation start states and the operation end states.
Preferably, of state variables specifying a state of the logic circuit block, any state variable that affects an output signal used to recognize an output instruction included in the input/output instruction information is selected as a control variable, and one or more states specified by the selected control variable are set as the operation start states and the operation end states in the state setting step.
Preferably, of the one or more states designated by the control variable, states where all or at least one of the control variables have the same value are regarded as a single state when the operation start states and the operation end states are set in the state setting step.
Preferably, in the state setting step, any state variable that contributes to updating of the control variable in one-clock operation of the RT-level model is also selected as the control variable.